1. Field of the Invention
The present invention relates to digital logic gate circuits which employ transistors as the active switching elements, and more particularly to such gate circuits wherein a change of logic state may cause transient variations of the potential of the internal voltage supply lines of the circuit relative to the external voltage supply to which the circuit is connected. Such variations are most troublesome in the low potential or ground line, being generally referred to as ground "bounce", and if excessive will result in erroneous logic signals at the load driven by the gate circuit.
2. Description of the Related Art
Various types of digital gate circuits are known in the art which employ transistors as the active switching elements for producing a logic "1" or "0" output, depending on the logic value of a control signal supplied to the circuit. One type of gate employs TTL logic, the output logic signal being produced at the juncture of a "pull-down" transistor and a "pull-up" transistor. Those are so-named because the former serves to bring the output signal down to the internal ground potential of the circuit and the latter brings the output signal up to a potential approaching that of the external voltage supply to which the circuit is connected. When positive logic is employed the ground potential corresponds to a logic "0" and the high potential to a logic "1". For simplicity of description that will be assumed herein, but it will be evident that negative logic could equally well be employed wherein the low potential would correspond to a logic "1" and the high potential to a logic "0".
A problem with TTL logic is that the pull-down transistor may be driven into saturation during turn-on, which limits its turn-off speed due to storage of minority carriers in the base zone. In Schottky logic families, to prevent saturation a Schottky barrier diode is connected between the base and collector of the transistor and serves to clamp the base current as saturation is approached.
Saturation is avoided in gate circuits which employ ECL logic, wherein the output stage is a single transistor which operates in the active region between saturation and cutoff to produce an output logic signal of a binary value dependent on whether the logic input control signal supplied to the circuit is high ("1") or low ("0").
Selection of the logic state to be established in the output stage in response to the logic input control signal is effected by a control transistor coupled to such stage and which renders it either more conductive or less conductive depending on the logic value of such control signal. In TTL logic the input control signal may be produced by an input circuit configured to provide a given logic function; e.g., AND, OR, NAND, etc, among a number of inputs thereto. In ECL logic the input circuit may comprise several transistors which receive respective logic signals at their bases and which have their emitters connected in common to a constant current source which also supplies current to the emitter of the control transistor of the gate circuit.
The basic features of a TTL logic gate are shown, for example, in FIG. 1 of U.S. Pat. No. 4,287,433, issued Sept. 1, 1981, as well as in FIG. 1 of U.S. Pat. No. 4,584,490, issued Apr. 22, 1986. The problem of transient ground bounce during high speed transitions between logic states of a TTL logic gate circuit is dealt with in U.S. Pat. No. 4,855,622, issued Aug. 8, 1989. This occurs because the transistors in the pull-up and pull-down stages may both be conductive for a brief interval during a logic state transition, and also because of transient currents produced in such stages due to the capacitance of the load driven by the logic gate. The resistance and inductance of the lines by which the gate circuit is connected to the external voltage supply and to the load are also contributing factors. Such patent teaches to limit ground bounce by providing a buffer circuit for the TTL gate which provides a controlled ramp output and includes means for limiting current between such output and the external ground.
A high speed form of TTL logic gate, which includes clamping diodes to keep the pull-down transistor out of saturation, is disclosed in U.S. Pat. No. 4,501,976, issued Feb. 26, 1985, and such circuit is substantially as shown in FIG. 1 herein. All transistors and diodes therein except pull-up transistor Q2 are of the Schottky clamped type. For purposes of illustration all the transistors are shown as NPN type bipolar transistors.
The pull-up transistor Q2 and pull-down transistor Q1 are connected in series between the internal voltage supply line 1 of the circuit and the internal ground line 2. Supply line 1 is coupled to the high terminal of an external voltage supply V.sub.cc. Such coupling has inherent resistance and inductance which are represented by a resistor R.sub.v and inductor L.sub.v in series. The low or ground terminal of the external voltage supply V.sub.cc is coupled to the internal ground line 2. The inherent resistance and inductance of that coupling are represented by a resistor R.sub.g and inductor L.sub.g in series. The collector of transistor Q2 is coupled by a resistor 4 to supply line 1. The logic output signal of the circuit is produced at the junction 5 of transistors Q1 and Q2, which junction is coupled to an external load 7 across which such signal is produced as an output voltage V.sub.OUT. The latter coupling also has inherent resistance and inductance, which are represented as a resistor R.sub.o in series with a conductor L.sub.o.
The input logic control signal V.sub.IN supplied to the logic circuit is obtained from an input circuit (not shown) as described above, and is received at the base of a transistor Q3 which serves as the control transistor. The emitter of the control transistor Q3 is connected to the base of pull-down transistor Q1. The collector of control transistor Q3 is connected to supply line 1 by a resistor 9, and is further connected to the base of a transistor Q4 the emitter of which is connected to the base of pull-up transistor Q2. The collector of transistor Q4 is connected to the collector of transistor Q2, and the emitter of transistor Q4 is connected to internal ground line 3 by a resistor 11. Transistors Q2 and Q4 thereby form a Darlington pair, which provides a high current gain between the base of the first Darlington transistor Q4 and the emitter of the second Darlington transistor Q2. A diode 13 is connected between the base of transistor Q2 and the collecter of transistor Q3, and speeds turn-off of the Darlington pair when the input logic control signal V.sub.IN at the base of transistor Q3 switches from a "0" to a "1". The emitter of transistor Q3 is returned to internal ground line 2 by a resistor 14 in series with a diode 15 which speeds turn-off of transistor Q1 when the input logic signal V.sub.IN changes from a "1" to a "0".
In operation, if the input logic control signal V.sub.in is a "0" it will cause control transistor Q3 to turn off. The emitter thereof then drops towards the potential of internal ground line 2 and so causes pull-down transistor Q1 to turn off. The potential at junction point 5, which is at the collecter of transistor Q1, is thereby isolated from ground. Turn-off of transistor Q3 also causes its collector voltage to rise, thereby turning on transistor Q4 which in turn causes turn-on of its Darlington pair pull-up transistor Q2. The potential at the emitter of transistor Q2 thereby rises nearly to that of supply line 1 less the base-emitter voltages of transistors Q4 and Q2, resulting in a logic "1" output signal V.sub.OUT at load 7. When the input logic control signal V.sub.IN changes to a "1" it cause control transistor Q3 to turn on. Its emitter voltage therefore rises, turning on pull-down transistor Q1. At the same time, the collector voltage of transistor Q3 falls, turning off both of Darlington transistors Q2 and Q4. Junction point 5 is thereby isolated from voltage supply line 1, but is connected by transistor Q1 to the internal ground line 2. A logic "0" output signal V.sub.OUT is thereby produced at load 7.
A problem with this circuit is that during each switch-over between the "1" and "0" logic state there is a brief interval during which transistors Q1 and Q2 are both conductive. A large feed-through current then is drawn from voltage source V.sub.cc to its ground return in the path through inductor L.sub.v and resistor R.sub.v, transistors Q2 and Q1, and resistor R.sub.g and inductor L.sub.g In addition, even after one of transistors Q1 and Q2 turns off, the resistor R.sub.O and inductor L.sub.O will maintain the current then existing therein for a transient interval and so delay a change in the output logic signal V.sub.O. A further factor is that if load 7 has significant capacitance there will be large charge and discharge currents through transistors Q1 and Q2. If the logic circuit is designed for switching logic signals to a load requiring significant current, such transient capacitive currents can reach several hundred milliamperes. The transient voltage drop produced by such currents in the various resistive and inductive couplings to the external voltage supply and its ground return, and also in the couplings to the external load, causes the potential of internal supply line 1 and internal ground line 2 to change or "bounce" relative to the external ground. The peak ground bounce voltage subtracts directly from the noise rejection margins of the logic control signal supplied to the circuit, since such signal represents a definite potential with respect to the external ground. Consequently, in extreme cases the ground bounce voltage can effectively cause an input logic "0" control signal to appear to be a "1", and vice versa. This, of course, will result in an incorrect logic value of the output signal produced by the gating circuit. The same problem is also present in ECL and other types of logic gating circuits which have an output stage including a transistor which switches between a high and a low conductive state.
It is known from FIG. 2 of U.S. Pat. No. 4287433 to shunt the base-emitter path of the pull-down transistor Q1 of a TTL gate circuit with the collector-emitter path of a further transistor in series with a resistor, to thereby provide "squaring" of the logic output signal at the collector of transistor Q1. A similar arrangement is shown in U.S. Pat. No. Re. 27,803. However, such patents do not deal with the problem of transient changes in potential of the internal supply and ground lines due to excessive current through the pull-up and pull-down output transistors.
FIG. 2 is a circuit diagram of a typical ECL gate. It includes an output transistor Q5 which has its emitter connected by a resistor 29 to an internal V.sub.EE line 2 which is at a negative potential relative to the internal V.sub.cc line. The emitter of transistor Q5 drives a load 7 across which the output signal V.sub.OUT of the gate circuit is produced. The input logic control signal V.sub.IN is applied to the base of an input transistor Q7 the emitter of which is connected in common with the emitter of a control transistor Q9 to a constant current source 25. Such a current source may simply be a resistor of suitable resistance. The collector of transistor Q7 is returned to the internal V.sub.cc line 1, and the collector of control transistor Q9 is connected to line 1 by a resistor 30. The base of transistor Q9 is connected to a source of a constant reference volta V.sub.R between the V.sub.cc and V.sub.EE levels. Transistors Q7 and Q9 thereby form a differential amplifier for the input logic control signal V.sub.IN, producing an output at the collector of control transistor Q9 which is coupled to the base of output transistor Q5.
When the input logic control signal V.sub.IN is a logic "0", transistor Q7 is off and the current from current source 25 all flows through transistor Q9. The collector voltage of transistor Q9 therefore falls, causing the emitter of output transistor Q5 to fall toward the V.sub.EE level. A "0" logic signal, at the internal V.sub.EE level, is then produced at the emitter of transistor Q5 and so the output signal V.sub.OUT of the logic gate is a "0". If the input logic control signal V.sub.IN goes high (a logic "1"), transistor Q7 will turn on. That reduces the emitter-collector current of transistor Q9, causing its collector voltage to rise and thereby render output transistor Q5 more conductive. The emitter voltage of transistor Q5 therefore rises, and so the output signal V.sub.OUT across external load 7 becomes a logic "1".